1. Field of the Invention
The present invention relates generally to polishing pads, particularly to those useful in semiconductor device manufacturing.
2. Discussion of Related Art
When a high degree of planarity and smoothness is required, polishing pad surfaces must be generally free from significant defects and irregularities, and polishing pads must be of uniform thickness. Large, substantially uniform, defect-free polishing pads are generally difficult to manufacture. Many conventional pad manufacturing processes result in large unusable portions of material. In addition, pad size is typically limited by pad manufacturing equipment capabilities and pad material limitations. As pad size increases, unwanted variations are common. By producing large polishing pads from smaller tiles these problems can typically be minimized or overcome. As discussed below, there are also other benefits of forming pads by tiling.
U.S. Pat. No. 5,212,910 describes a composite pad comprising a first layer of elastic material, a second, stiff layer and a third layer optimized for slurry transport. The second layer is segmented into individual sections physically isolated from one another in the lateral dimension. The segments, combined with the cushioning of the first layer, enable the pad to conform to longitudinal gradations across the wafer.